The faster and faster growth of the internet based solutions (IP and packet-based) is driving a need for big transfer capability in electronics market. Ethernet is really a family of networking standards that dictates how data should travel across a distance, thanks to the availability of low cost solutions and to the huge diffusion in many electronic devices.

The demand for higher speed and performance drives a scenario where higher-capacity ports are displacing lower-capacity ports. From the old 10Mb/s devices, the data rate speed increased to 100Mb/s; nowadays 1Gb/s solutions are present in the market and the research is moving toward 10Gb/s.

The project is addressing the optimization of the present design (up to 1Gb/s) and the study and research for next generation implementation (10Gb/s). The design is challenging since this application is the only one among wired links with multi-levels data transmission, aiming to overcome the speed limit of the copper cables. The project addresses the following areas of studio:

• Analog circuit design
• Feasibility studies for power/area optimization and to prove innovative solutions
• Design specification definition with the architecture team
• Mixed-signal (analog-digital) simulation for the interfaces analysis
• Analog design verification for validation and sign-off
• Measurements and characterization of the prototypes

The potential application are Ethernet wired links, such as the IP networks, routers, switches, data centers, and a lot of variety of user terminals (PCs, TVs, decoders, household electrical appliances, alarm systems, internet remote control, and so on).

This project is lead within ST High Speed Interface IP team, with a direct link to ST Network & Storage Division, both in the Computer & Communication Infrastructure Product Group.

This activity is pursued by the Gigabit Ethernet team.
For further details you can contact Prof. F.Svelto or ST team leader G.Albasini.